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Feasibility of Novel Deca-Nanometer Vertical MOSFETs for Low-cost Radio Frequency Circuit Application

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This research aims to investigate the use of CMOS-compatible vertical MOSFETs for the implementation of medium-power RF circuits, opening the way to higher integration of RF systems. Vertical transistors are currently of interest because they offer an alternative route to ultra-short channel MOS transistors with relaxed lithography requirements (and hence considerably lower costs), decouple gate length from the packing density and provide improved current drive per unit silicon area compared with conventional lateral CMOS. In this research approaches will be investigated that deliver these benefits through the integration of vertical MOSFETs in a mature CMOS technology with minimum additional masks above those required for standard 0.5 micron CMOS. The intention is to appraise in depth, the feasibility of this novel technology for the manufacture of low-cost RF solutions.

The challenges of vertical MOSFETs for RF applications are high overlap capacitance, short channel effects, susceptibility to dry etch damage and the lack of an appropriate silicidation technology. A detail investigation has been done to deliver solutions for challenges like overlap capacitance, short channel effects and dry etch damage. A CMOS compatible Fillet Local Oxidation (FILOX) process has been developed and novel structures (frame gate) proposed to reduce the overlap capacitance and to eliminate dry etch damage associated device degradation. The resulting transistors are found to have significantly improved immunity to short channel effects, with near ideal sub-threshold slopes of 70 to 80 mV/decade, and DIBL of 30 to 35 mV/V. More recently we have developed for the first time a silicidation technology for surround gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for the silicidation. For a 120 nm channel length, silicided frame gate vertical nMOSFETs show a 30% improvement in the drive current with an excellent sub-threshold slope of 78mV/decade and a DIBL of 30 mV/V. For an 80 nm channel length, a 43% improvement in the drive current is obtained. Vertical transistors with our FILOX process and silicidation resulted in a transistor with low overlap capacitance and high transistor transconductance. While conventional planar nMOS devices exhibit a fT of 10 GHZ in a 0.5 micron technology node, our vertical nMOS devices fabricated by above mentioned FILOX and silicidation process demonstrating a fT of 20 GHZ in the same technology node. We are currently investigating several RF circuits with verical nMOS devices aimed at the highly lucrative 1-10 GHz market.

Type: Normal Research Project
Research Groups: Nano Research Group, Southampton Nanofabrication Centre
Theme: Nanoelectronics
Dates: 1st March 2007 to 1st March 2010

Keywords

Partners

  • University of Liverpool

Funding

  • EPSRC

Principal Investigators

Other Investigators

URI: http://id.ecs.soton.ac.uk/project/654
RDF: http://rdf.ecs.soton.ac.uk/project/654

More information

Associated Publications

Number of items: 12.

Hakim, M. M. A., Tan, L., Buiu, O., White, W. R., Hall, S. and Ashburn, P. (2009) Improved sub-threshold slope in short channel vertical MOSFETs using FILOX oxidation. Solid State Electronics, 53 . pp. 753-759.

Hakim, M. M. A., Mallik, K., de-Groot, C. H., White, W. R., Tan , L., Hall, S. and Ashburn, P. (2009) A Self-Aligned Silicidation Technology for Surround-Gate Vertical MOSFETS. In: The 39th European Solid-State Device Research Conference (ESSDERC 2009), 14-18th September, Athens, Greece..

Tan, L., Hakim, M. M. A., Connor, S., Bousquet, A., White, W. R., Ashburn, P. and Hall, S. (2009) Characterisation of CMOS Compatible Vertical MOSFETs with New
Architectures through EKV Parameter Extraction and RF Measurement. In: 10th International Conference on ULtimate Integration of Silicon (ULIS), 18-20, March, Aachen, Germany.

Hakim, M. M. A., Tan, L., Uchino, T., Buiu, O., White, W. R., Hall, S. and Ashburn, P. (2008) Improved Sub-threshold Slope in RF Vertical MOSFETS using a Frame Gate Architecture. In: 38th European Solid-State Device Research Conference (ESSDERC 2008), 15-19th September, Edinburg, UK.

Tan, L., Hakim, M. M. A., Uchino, T., Redman-White, W., Ashburn, P. and Hall, S. (2008) Asymmetrical IV characteristics and junction regions in implantation defined surround gate vertical MOSFETs. In: 9th International Conference on Solid State and Integrated Circuit Technology (ICSICT), Beijing, China.

Tan, L., Hall, S., Buiu, O., Hakim, M. M. A., Uchino, T., White, W. R. and Ashburn, P. (2008) Series Resistance in Vertical MOSFETs with Reduced
Drain/Source Overlap Capacitance. In: 9th International Conference on Ultimate Integration of Silicon, 2008. ULIS 2008. , 12-14th March, Udine, Italy.

Hall, S., Tan, L., Buiu, O., Hakim, M. M. A., Uchino, T., Ashburn, P. and White, W. R. (2007) VERTICAL MOSFETs FOR HIGH PERFORMANCE, LOW COST CMOS. In: International Semiconductor Conference, CAS, 17, September.

Gili, E., Kunz, V. D., Uchino, T., Hakim, M. M. A., Groot, C. H. d., Ashburn, P. and Hall, S. (2006) Asymmetric Gate-Induced Drain Leakage and
Body Leakage in Vertical MOSFETs With
Reduced Parasitic Capacitance. IEEE TRANSACTIONS ON ELECTRON DEVICES, 53 (5). pp. 1080-1087. ISSN TED.2006.872361

Gili, E., Uchino, T., Hakim, M. M. A., Groot, C. H. d., Buiu,, O., Hall, S. and Ashburn, P. (2006) Shallow Junctions on Pillar Sidewalls for
Sub-100-nm Vertical MOSFETs. IEEE ELECTRON DEVICE LETTERS, 27 (8). pp. 692-695.

Hakim, M. M. A., Groot, C. H. d., Gili, E., Uchino, T., Hall , S. and Ashburn, P. (2006) Depletion-Isolation Effect in Vertical MOSFETs
During the Transition From Partial to
Fully Depleted Operation. IEEE Transaction on Electron Devices, 53 (4). pp. 929-933.

Gili, E., Uchino, T., Hakim, M. M. A., Groot, C. H. D., Ashburn, P. and Hall, S. (2005) A new approach to the fabrication of CMOS compatible vertical MOSFETs incorporating a dielectric pocket. In: Proceedings of 6th International Conference on Ultimate Integration of Silicon (ULIS). pp. 127-130.

Hakim, M. M. A., Groot, C. H. D., Gili, E., Uchino, T., Hall, S. and Ashburn, P. (2005) Effect of transition from PD to FD operation on the depletion isolation effect in vertical MOSFETs. In: 6th International Conference on ULtimate Integration of Silicon (ULIS), Bologna, Italy. pp. 131-134.

This list was generated on Fri Feb 10 01:00:03 2012 GMT.

Publications included from http://eprints.ecs.soton.ac.uk/view/projects/654.include.