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Spectrum Monitor for Cognitive Radio

Test chip (Integrated BPF and in wide tuning range PLL on standard digital CMOS technology)

In this project, the spectrum monitor for cognitive radio is explored. The main challenge of the cognitive radio application is to draw a spectrum map covering a wide range of frequency fast and accurate enough while consuming lower power and keeping lower cost compared with main transceiver circuits, hence a unique receiver (spectrum monitor) must be designed. In this project, the target frequency range covers from 2GHz to 5GHz, which is a potential band for the cognitive radio, and the sensitivity/frequency resolution is to set to -80dBm/200kHz for strong signal detection of most communication systems.

To design such a RF system from system level, a novel method involving the concept of figure of merit is adopted to find a proper solution to balance different aspects of the receiver, including the performance, the power and the cost. By analysing the theory and the statistics collection for key blocks in RF system through years, this method can provide a general guide of trade-off between the power consumption and performance of receiver for the following several years and the trade-off among the performance.

Because of its unique application, some of the key blocks of the spectrum monitor are different from those in popular receivers. the low cost and high integration requirement prompt the design of a lumped element on chip passive band pass filter for IF selection. And a ring oscillator based digital tuning integer frequency synthesizer is designed to fulfill the wide tunig range and the low cost specifications. These components are designed on the 130nm standard digital CMOS technology to keep the lowest cost for portable devices.

The entire spectrum monitor system design involves the specially designed blocks(PLL, BPF) in circuit level simulations, fabrication and measurements as well as the collected existing blocks(such as wideband LNA, high linearity mixer, the base band low pass filter and ADC) since these components are more conventional. The trade-off and evaluation of the receiver solutions will be provided and analyzed.

Type: Postgraduate Research
Research Group: Nano Research Group
Theme: System design and RF
Dates: 1st October 2006 to 30th September 2009



Principal Investigators

URI: http://id.ecs.soton.ac.uk/project/666
RDF: http://rdf.ecs.soton.ac.uk/project/666

More information

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