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This is now an inactive research group it's members have moved on. You can find them at their new research groups:

ECS Intranet:
Paradigm Unifying System Specification Environments for proven Electronic design

The objective of PUSSEE is to introduce the formal proof of system properties throughout a modular system design methodology that integrates sub-systems co-verification with system refinement and reusability of virtual system components. This will be done by combining the UML and B languages to allow the verification of system specifications through the composition of proven sub-systems (in particular interfaces, using the VSIA/SLIF standard). The link of B with C, VHDL and SystemC will extend the correct-by-construction design process to lower system-on-chip (SoC) development stages. Prototype tools will be developed for the code generation from UML and B, and existing B verification tools will be extended to support IP reuse, according to the VSI Alliance work. The methodology and tools will be validated through the development of three industrial applications: a wireless mobile terminal, an IP encryption module for secure data transmission through internet and a network management module for automobiles.

Homepage: http://www.keesda.com/pussee/
Type: Normal Research Project
Themes: Design, Automation, Simulation and Optimisation, Formal Methods, Systems Engineering
Dates: 1st January 2002 to 31st December 2003



Other Investigators

URI: http://id.ecs.soton.ac.uk/project/95
RDF: http://rdf.ecs.soton.ac.uk/project/95

More information

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